Essays --

The CMOS technology plays a major role on theperformance of micro butt againstors on very large scale integ postdcircuit chips. The rapid exploitation in CMOS technology with theshrinking electronic transistor size towards 16nm has allowed for positioning of some(prenominal) billions of transistors on a singlemicroprocessor chip. This also leads to reduce the delay of logical systemgates in the order of pico seconds. One such(prenominal) method to reformthe performance of microprocessor is to optimize the timingperformance of dynamic circuits. In this penning a full(a) common vipercircuit is designed and simulated apply appraise detection stewardtechnique with L=0.12m technology and VDD=1.2 V forimproving the timing and fraudulent scheme tolerance also the noise tolerancecharacteristics of the full common viper circuit designed employ ratesensing keeper is compared with twin transistor based full addercircuit.Keywords Bias,Domino logic, noise tolerance, rate sensing,timin g optimization.I. INTRODUCTIONHE rapid advancement in semiconductor technology withthe shrinking transistor size towards 16nm has allowed forplacement of several billion transistors on a singlemicroprocessor chip1. CMOS technology plays a major roleon the performance of VLSI microprocessors 2.The timingperformance of the microprocessor drive out be improved by usingdynamic circuits in microprocessors 3. yet the usage ofdynamic circuits in microprocessors is limited due to manychallenges including transistor sizing, charge sharing, leakagecurrent, noise immunity and environmental and semiconductorprocess variations etc 4.Timing optimization of dynamiccircuits can be achieved through several methods such astransistor sizing, using multiple threshold voltagesetc.5,6,7.The aggressive grading of transistors andinterc... ... andthe experimental results shows that the full adder circuitdesigned using rate sensing keeper transistor technique givessuperior performance compared to the new(prenominal) alternatives suchas Conditional keeper (CKP) and current mirror-based keeper(LCR).Fig.22. getup noise Vs Vbias characteristics of full adder using Rate SensingKeeper techniqueIV. CONCLUSIONIn this paper the performance of a full adder circuitdesigned using rate sensing keeper transistor technique isanalyzed in detail and its performance is compared with otherfull adder circuits. The full adder circuit is simulated usingL=0.12m technology along with supply voltage VDD=1.2V.The experimental results shows that the full adder circuitdesigned using rate sensing keeper transistor technique givessuperior performance compared to full adder circuits designedusing conventional domino techniques.